1. Field of the Invention
The present invention relates to a method for modeling a semiconductor device process, particularly to a modeling method of impurity diffusion in a semiconductor, and a reverse snort channel effect of a threshold voltage of a MOS type field-effect transistor (MOSFET).
This application claims priority under 35 U.S.C. 119 to Japanese Application Serial Number 246268/2001, filed May 29, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 9 shows a mechanism of impurity diffusion in a case in which an excessive point defect exists in a semiconductor. An excessive point defect I is generated mainly in a high-dosage ion-implantation process. Particularly, the excessive point defect I generated in a source and drain (S/D) ion-implantation process of the MOSFET forms a pair with an impurity A by an immediately subsequent thermal treatment for allowing an ion to diffuse, and a pair AI of the impurity and point defect repeats separation and coupling, and diffuses. Thereafter, pairs AV and AI reach an interface between Si and SiO2, the point defect I of the pair disappears, and the impurity A having formed the pair piles up. Additionally, V denotes a void, IV denotes a pair of the point defect and void, and AV denotes a pair of the impurity and void.
FIGS. 10A–10C respectively show a relation between a distance of a channel direction Distance, and an impurity density Conc. in a case in which a gate length is set to 2.03 μm, 0.52 μm, and 0.21 μm. In the drawing, a portion having a low impurity density corresponds to a channel, and a rise of the impurity density by impurity pileup is seen in portions corresponding to the drain and source on opposite sides of the channel.
A pileup amount is largest in a gate end close to an S/D implantation position, and decreases toward the channel. A reverse short channel effect of a threshold voltage of the MOSFET (a phenomenon in which the threshold voltage increases with a shorter gate length) is deemed to occur by the pileup as a main factor.
FIG. 11 shows a relation between a gate length Lg and a threshold voltage Vth when a substrate bias VB is 0V, −3V, −5V. In a semiconductor device, when a device dimension is reduced so as to enhance a response speed and integration degree, the gate length is generally and accordingly shortened.
On the other hand, the threshold voltage Vth is preferably constant regardless of the gate length Lg in a circuit design. However, the reverse short channel effect is seen. That is, when the gate length Lg is shortened (about 1 μm or less in FIG. 11), the threshold voltage Vth vertically fluctuates.
A conventional model for describing impurity diffusion in the semiconductor is roughly classified in three. That is, a first model is a method including: setting an analysis object region; solving one diffusion equation with respect to each impurity; and calculating an impurity distribution in the semiconductor (hereinafter referred to as a Fair model). A second model is a method including: setting the analysis object region; assuming that the point defect and impurity form a pair and diffuse, and solving respective diffusion equations with respect to the point defect, and the pair of impurity and point defect; and calculating the impurity distribution in the semiconductor (hereinafter referred to as a pair diffusion model). A third model is a simple model for setting an analysis region, and simply taking the effect in a frame of the Fair model without solving the diffusion equation associated with the point defect.
The following equations are equations for use in using the Fair model and pair diffusion model to obtain the impurity distribution in the semiconductor.
Fair Model∂CA/∂t=−∇JA  (Equation 12)
Pair Diffusion Model∂CI/∂t+Σ∂CAI/∂t=−∇JI−Σ∇JAI−RI,V+RIV  (Equation 13)∂CV/∂t+Σ∂CAV/∂t=−∇JV−Σ∇JAV−RI,V+RIV  (Equation 14)∂CAtotal/∂t=∇{DAICAtotal(CI/CI*)∇(log(pCAtotalCI/CI*ni)}+∇{DAVCAtotal(CV/CV*)∇(log(pCAtotalCV/CV*ni)}  (Equation 15)
Here,
C: density (cm−3) CAtotal=ΣCA+ΣCAI+ΣCAV 
J: flux (cm−2/s)
R: re-coupling speed (cm−3/s)
P: carrier density (cm−3)
C*: equilibrium density (cm−3)
ni: intrinsic carrier density (cm−3)
D: diffusion constant
A: all dopant species
I: interstitial
V: vacancy
AI: pair of dopant species and interstitial
IV: pair of interstitial and vacancy
AV: pair of dopant species and vacancy
As shown above, for the first Fair model, since the number of equations to be solved is small, a calculation time is short, and the model can advantageously easily be handled. On the other hand, an influence of the point defect with respect to the impurity diffusion is not handled, and therefore there is a disadvantage that the impurity pileup in the interface of Si and SiO2 cannot be reproduced.
In the second pair diffusion model, since the influence of the point defect with respect to the impurity diffusion is strictly handled, simulation can advantageously be performed with a high precision. On the other hand, when the number of impurities increases, the number of equations to be solved also increases, and the calculation time disadvantageously increases.
The third simple model has an advantage that tradeoff of the calculation time and simulation precision can well be absorbed, but a degree of reproduction of an application range of the model and process dependence is a key.
Examples of the simple model include a simple model disclosed, for example, in Japanese Patent Application Laid-Open No. 084716/2000. FIG. 12 is an explanatory view of the simple model, FIG. 13 is a diagram showing a lateral distribution of the impurity pileup in an end of a gate electrode in the semiconductor substrate, and FIG. 14 is a flowchart showing the simple model.
In FIG. 12, C(xi,yj) denotes the impurity density of each cell, ΔC(xi,yj) denotes the impurity density which decreases in each cell, and ΔS(xi,yj) denotes an area of each cell. An amount of the impurity included in the cell (x1,y1) at the interface is C(x1,y1)ΔS(x1,y1) before the diffusion, and C(x1,y1)ΔS(x1,y1)+ΔC(xi,yj)ΔS(xi,yj) after the diffusion. In FIG. 13, Cint(x) denotes the impurity pileup amount in the interface, and Cpile denotes the impurity pileup amount in a region in which a gate 10 is not disposed. FIG. 13 shows that the pileup amount of the impurity decreases according to Equation 16 in a portion closer to a middle portion of the gate 10. Moreover, the impurity pileup amount is constant at Cpile in the region where the gate 10 is not disposed.Cint (x)=Cpile exp(−x/λint)  (Equation 16)
In FIG. 14, t denotes time. Particularly, tTED denotes a transient enhanced diffusion (TED) duration.
As shown in FIGS. 12, 13 and 14, first an Si layer is divided into a plurality of cells. For the impurity pileup in the interface of Si and SiO2 which cannot be reproduced by the Fair model, instead of solving the diffusion equation associated with the point defect, a part of an impurity amount of a substrate region is moved to the interface of Si and SiO2 and constitutes the pileup. An impurity movement mass is used as a function of a distance of a noted interface position to the cell of the substrate region in a method for use.
When the diffusion model is used to model the reverse short channel effect of the threshold voltage, for example, the following methods are used:
(1) a method of using the pair diffusion model to calculate the impurity distribution, and calculating an electric property in an unchanged state; and
(2) a method of using the simple model to calculate the impurity distribution, and calculating the electric property in the unchanged state.
However, the aforementioned methods have some problems.
1. In the pair diffusion model, the calculation time increases. Therefore, when simulations such as sensitivity analysis among the process, device, and circuit, process optimization, process dispersion analysis, and calibration of a model parameter need to be executed a plurality of times, it is difficult to use the pair diffusion model.
2. In the conventional simple model, since the calculation of a mass of impurity moving to the interface of Si and SiO2 is represented by the function only of the interface position and the distance to the cell of the substrate region, dependence of the S/D process on an impurity density re-distribution cannot be reproduced.
3. Moreover, in the conventional simple model, a shape of the impurity pileup in the interface is determined beforehand. Therefore, there is a problem that the dependence of the process on the shape of the pileup cannot be predicted.